![]() There are simple shift register-based n-bit counters with a few XOR gates that behave pseudo-randomly. Linear feedback shift register (LFSR) is the basic building block of the communication system used in different coding, error detection and correction codes, such as gold, low-density parity check (LDPC), polar, and turbo codes. From the simulation results, it is clearly observed that 62.12% power reduced compared to conventional LFSR, 26.71% power reduced compared to GDI, 59.40% delay reduced compared to conventional and 66.75 % delay reduced compared to GDI. The proposed hybrid 4-bit LFSR model achieved better performances of delay and power parameters as compared with other existing models. The performances of area, power and delay parameters were obtained using Cadence Spectra simulator, Digital Schematic and Micro Wind tools. The proposed hybrid 4-bit LFSR can be designed using both conventional D flip-flop and GDI based XOR gate using Cadence Virtuoso with 90nm technology library. This paper proposed hybrid 4-bit LFSR which is the combination of both conventional and GDI models. So, we have to reduce the transistor count to reduce power dissipation. But GDI based Linear Feedback Shift Register (LFSR) needs a larger number of transistors for the construction of D flip-flop due to which the area required will be more than the conventional model. Gate Diffusion Input (GDI) technique reduces the power, delay and also maintains a less complex logic design. ![]()
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